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To support the ever-growing demand for faster, energy-efficient computation, more aggressive scaling of the transistor is required. Two-dimensional (2D) transition metal dichalcogenides (TMDs), with their ultra-thin body, excellent electrostatic gate control, and absence of surface dangling bonds, allow for extreme scaling of the channel region without compromising the mobility. New device geometries, such as stacked nanosheets with multiple parallel channels for carrier flow, can facilitate higher drive currents to enable ultra-fast switches, and TMDs are an ideal candidate for that type of next generation front-end-of-line field effect transistor (FET). TMDs are also promising for monolithic 3D (M3D) integrated back-end-of-line FETs due to their ability to be grown at low temperature and with less regard to lattice matching through van der Waals (vdW) epitaxy. To achieve TMD FETs with superior performance, two important challenges must be addressed: (1) complementary n- and p-type FETs with small and reliable threshold voltages are required for the reduction of dynamic and static power consumption per logic operation, and (2) contact resistance must be reduced significantly. We present here the underlying strengths and weaknesses of the wide variety of methods under investigation to provide scalable, stable, and controllable doping. It is our Perspective that of all the available doping methods, substitutional doping offers the ultimate solution for TMD-based transistors.

 

Near-perfect light absorbers (NPLAs), with absorbance,$${{{{{{{\mathcal{A}}}}}}}}$$$A$, of at least 99%, have a wide range of applications ranging from energy and sensing devices to stealth technologies and secure communications. Previous work on NPLAs has mainly relied upon plasmonic structures or patterned metasurfaces, which require complex nanolithography, limiting their practical applications, particularly for large-area platforms. Here, we use the exceptional band nesting effect in TMDs, combined with a Salisbury screen geometry, to demonstrate NPLAs using only two or three uniform atomic layers of transition metal dichalcogenides (TMDs). The key innovation in our design, verified using theoretical calculations, is to stack monolayer TMDs in such a way as to minimize their interlayer coupling, thus preserving their strong band nesting properties. We experimentally demonstrate two feasible routes to controlling the interlayer coupling: twisted TMD bi-layers and TMD/buffer layer/TMD tri-layer heterostructures. Using these approaches, we demonstrate room-temperature values of$${{{{{{{\mathcal{A}}}}}}}}$$$A$=95% atλ=2.8 eV with theoretically predicted values as high as 99%. Moreover, the chemical variety of TMDs allows us to design NPLAs covering the entire visible range, paving the way for efficient atomically-thin optoelectronics.

 

Topological insulators open many avenues for designing future electronic devices. Using the Bardeen transfer Hamiltonian method, we calculate the current density of electron tunneling between two slabs of Bi2Se3. 3D TI tunnel diode current-voltage characteristics are calculated for different doping concentrations, tunnel barrier height and thickness, and 3D TI bandgap. The difference in the Fermi levels of the slabs determines the peak and trough voltages. The tunnel barrier width and height affect the magnitude of the current without affecting the shape of the current-voltage characteristics. The bandgap of the 3D TI determines the magnitude of the tunnel current, albeit at a lesser rate than the tunnel barrier potential, thus the device characteristics are robust under changing TI material. The high peak-to-trough ratio of 3D TI tunnel diodes, the controllabilty of the trough current location, and the simple construction provide advantages over other NDR devices. 

Keynote presentation for the NSF Future of Semiconductors workshop. 

Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS₂, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe₂transistors with impressive subthreshold slope (109 mV dec⁻¹) andI_ON/I_OFF(10⁶) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe₂in situbefore metallization, which minimizes subsequent reactions between Sc and WSe₂. Post metallization anneals in reducing environments (UHV, forming gas) degrade theI_ON/I_OFFby ~10³and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe₂, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe₂layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe₂Fermi level around individual Sc atoms in the WSe₂lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe₂transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe₂.